In the processing of semiconductor wafers the typically must be transported either between processes or to other facilities. The semiconductor wafers are fragile and damage to the surface of the wafers can make the wafer useless for the intended purpose. Because of the high potential for damage to the wafer the semiconductors must be packaged and transported to minimize harm. In transportation, multiple semiconductor wafers are stacked into a transportation container. There have been a number of containment products and patents have been sold and patented to try and minimize damage to these silicon wafers. Exemplary examples of patents covering these products are disclosed herein.
U.S. Pat. No. 6,193,068 issued Feb. 27, 2001 to Lee Lewis et al., and U.S. Pat. No. 6,341,695 issued Jan. 29, 2002 to Lee Lewis et al., disclose a containment device for retaining semiconductor wafers. This patent discloses two concentric walls on the top and bottom housings that nest to protect the semiconductor wafers. Double walls were designed to protect the wafers from the direct transmission of forces that may contact the outer wall. While the nesting walls provide protection from side impacts they do not provide flexibility to absorb and cushion a side impact or drop. The combination of an outer wall and a gap provide the protection. Damage may also occur if the force is such that the outer wall flexes enough to interfere with the inner wall, thereby damaging the wafers. That can cause the semiconductor wafers to shift and scratch.
U.S. Patent Publication Number U.S.2009/0095650 that was published on Apr. 16, 2009 to James D. Pylant et al., discloses a wafer container with staggered wall structure. In this published application the design is limited by the amount overlap of the inner and outer walls by the design of its staggered walls. The walls were limited to 5% overlap, with 95 percent of the outer wall not located in adjoining angular sectors. This and other top cover rotation locating mechanisms use either an inner surface of a feature on the top cover or an exterior surface of a feature on the top cover to secure the top cover in place and prevent rotation.
U.S. Pat. No. 6,550,619 issued Apr. 22, 2003 to Gregory W. Bores et al., discloses a shock resistant variable load tolerant wafer shipper. This patent uses four inner tapers walls with a variable amount of cushions placed between the semiconductor wafers to pack and cushion the semiconductor wafer. While this patent allows for a variable amount of semiconductor wafers to be packed within the shipper the cushioning relies on the variable amount of cushions placed between the semiconductor wafers to reduce damage.
U.S. Pat. No. 7,040,487 issued on May 9, 2006 to Michael Zabka et al., discloses a protective shipper with a corrugates inner containment lip. The corrugated inner lip provides multiple surfaces for the edges if the semiconductor wafers to make contact with, but because the edges are corrugated the tangential walls of the corrugation limit the flexing of the inner lips.
Some semiconductor wafer containers use a rotation locking design where the locating mechanism with an exclusive inner surface or exterior surface do not securely capture the wall that they are adjacent to in both directions of rotation. These features only stop rotation in only one direction. The features must rely on a sister feature to stop rotation in the opposite direction which is generally located farther away and allows for more manufacturing tolerance to build up since it is located at a greater distance. These deficiencies result in larger gaps between the plus and minus rotational limiting surfaces, thereby leading to more rotational movement.
There are a number of prior designs that use top cover orientation features with differing wall engagement angles or large latches as opposed to small slots. The new feature in this proposed wafer container allows improved orientation that is not found in the prior art.
There are a number of different holding and clamping features in wafer shipping containers. All of these prior designs rely on multiple parts to create a clamping lip. These designs have several drawbacks including but not limited to the parts not being rigid with respect to the bottom assembly because they must be sonic welded, bonded or snapped together and that secondary parts or assembly operations are more expensive to produce.
The engagement of latches that secure the top and bottom housings together have a number of limitations. Specifically, prior art latches provide a raised straight slope ramp. The raise straight sloped surface is susceptible to damage and also, the straight slope does not provide an ideal self gripping to engage between the top and bottom housings. The top cover orientation features use differing wall engagement angles or large latches as opposed to small slots as presented in this pending application.
What is needed is a semiconductor wafer container with improvements in side protection to the wafers, improved cover design to minimize rotation, a simplified top cover orientation mechanism and an improved bottom holding mechanism for automation. This pending application satisfies these requirements with novel improvements in the identified areas.